In electronic systems containing multiple integrated circuit (IC) components communicating with each other, it is necessary to synchronize the timing of signal transmission and receipt between components in order to avoid timing errors. Timing errors include one or more components failing to accurately interpret electronic signals as correct data. Many phenomena (physical conditions, digital logic errors, etc.) can result in timing errors particularly in systems that operate at speeds and/or have high data throughput rates, as is well known in the art. Typically, many IC components contain timing circuitry and logic devoted to minimizing timing errors. However, it is always desirable to minimize the physical chip area and the power consumed by IC components, especially by the area and power consumed by functions not directly related to the purpose of the system or component. This is particularly true of data storage (also referred to herein as memory) components. The cost of memory components is dramatically affected by increases in amounts of circuitry and area required that are not dedicated to data storage. In addition, extra power consumed that is not directly related to data storage makes a memory component less desirable than a memory component with similar data storage capacity and smaller power requirements. Therefore providing an efficient way of communicating with other system IC components while avoiding timing errors is an aspect of IC design for any type of IC, including memory components.
Another aspect of IC design is consideration of and compliance with published and recognized industry standards. Compliance with industry standards helps assure that different components for different purposes and from different manufacturers can operate correctly in an IC system.
FIG. 1 is a diagram of a computer system 100 showing various system components in the prior art. System 100 includes a graphics processing subsystem 101 coupled to a system bus 114. Also coupled to bus 114 are a central processing unit 116, a system memory 118, removable storage 122, and user input device 120. Subsystem 101 includes a graphics processing unit (GPU) 102, including a system interface 104, a memory interface 106, and a clock and data recovery unit (CDR) 105. System interface 104 includes circuitry, logic and physical pins for communicating with other system and subsystem components. As an example, DATA pins, command (CMD) pins, and address (ADDR) pins are shown. Subsystem 101 further includes a local memory 108, and a display interface 110. GPU 102 is an example of a special purpose processor within a computer system. GPU 102 accesses both its local memory 108 and other memory components coupled to bus 114, such as system memory 118, and possibly removable storage 122.
FIG. 2 is a diagram of particular system components in the prior art. GPU 104 communicates with a memory component 119. Memory component 119 may be included in either removable storage 122 or system memory 118, and is just one example of a memory component external to, but accessible to, GPU 102. In the example shown, memory component 119 is a dynamic random access memory DRAM component. DRAM 119 includes a command decoder 228, mode registers 226, and a “reference data” or REFD circuit 224. REFD circuit 224 receives a reference voltage on a REFD pin. In such a previous system, one method for synchronizing timing between GPU 102 and DRAM 119 involves examining the timing of READ data and using that to estimate WRITE timing. A clock signal is sent to DRAM 119, and READ data is returned. Based on the timing of that transaction, timing for a WRITE transaction is estimated. However, this method is rather inaccurate because the actual WRITE transaction is not being examined.
FIG. 5 is a diagram of a system component mode register in the prior art. This example includes some of the mode registers in a DRAM compliant with an existing GDDR standard. The GDDR5 standard is referred to here, but is not meant to be exclusive reference. The GDDR specification includes register that are configurable by a controlling component in a system. For example, mode register 8 (MR8) includes blank data fields to signify fields that can be overwritten by a controlling component. FIG. 6 is a diagram of a definition mode register 6 of FIG. 5 in the prior art. Mode register 6 (MR6) includes fields to configure the VREF function of DRAM 119.
It would be desirable for an IC to include an efficient method and apparatus for efficiently providing for minimizing timing error in an IC system while considering applicable industry standards.